We have studied nanocrystal memory arrays with 2.56×105 cells (256kb) in which Si nanocrystals have been obtained by CVD deposition on a 4nm tunnel oxide. The cells in the array are programmed and erased by electron tunneling through the SiO2 dielectric. We find that the threshold voltage distribution has little spread. In addition the arrays are also very robust with respect to drain stress and show good retention.
|Numero di pagine||4|
|Stato di pubblicazione||Published - 2002|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality