In this paper we analyse the operation of a fully digital Phase Lock Loop (PLL) in a false lock regime, using real data. The issue has been noticed while we were testing performance of our software receiver ina moving user scenario. While the phenomenon of false lock has been described in other papers about PLLs, our intent is to describe a practical, and in our opinion interesting, issue we encountered and how we got overit.
|Numero di pagine||0|
|Stato di pubblicazione||Published - 2009|