On the Theoretical Limits of Noise-Gain-Mismatch Tradeoff in the Design of Multi-Stage Cascaded Transistor Amplifiers

Bruno Di Maio, Enrico Calandra, Daniele Lupo

Risultato della ricerca: Paper

2 Citazioni (Scopus)

Abstract

The problem of evaluating the limit performances of cascaded single-ended multi-stage transistor amplifiers is addressed. In particular, a theoretically rigorous approach is proposed for the determination of a family of optimal design curves (ODC's) which express the best (maximum optimal) noise-gain tradeoff that can be achieved - at each operating frequency - when a simultaneous constraint on amplifier input VSWR is accounted for.
Lingua originaleEnglish
Stato di pubblicazionePublished - 2007

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Transistors
Optimal design

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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On the Theoretical Limits of Noise-Gain-Mismatch Tradeoff in the Design of Multi-Stage Cascaded Transistor Amplifiers. / Di Maio, Bruno; Calandra, Enrico; Lupo, Daniele.

2007.

Risultato della ricerca: Paper

Di Maio, B, Calandra, E & Lupo, D 2007, 'On the Theoretical Limits of Noise-Gain-Mismatch Tradeoff in the Design of Multi-Stage Cascaded Transistor Amplifiers'.
Di Maio B, Calandra E, Lupo D. On the Theoretical Limits of Noise-Gain-Mismatch Tradeoff in the Design of Multi-Stage Cascaded Transistor Amplifiers. 2007.
Di Maio, Bruno ; Calandra, Enrico ; Lupo, Daniele. / On the Theoretical Limits of Noise-Gain-Mismatch Tradeoff in the Design of Multi-Stage Cascaded Transistor Amplifiers.
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AU - Lupo, Daniele

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N2 - The problem of evaluating the limit performances of cascaded single-ended multi-stage transistor amplifiers is addressed. In particular, a theoretically rigorous approach is proposed for the determination of a family of optimal design curves (ODC's) which express the best (maximum optimal) noise-gain tradeoff that can be achieved - at each operating frequency - when a simultaneous constraint on amplifier input VSWR is accounted for.

AB - The problem of evaluating the limit performances of cascaded single-ended multi-stage transistor amplifiers is addressed. In particular, a theoretically rigorous approach is proposed for the determination of a family of optimal design curves (ODC's) which express the best (maximum optimal) noise-gain tradeoff that can be achieved - at each operating frequency - when a simultaneous constraint on amplifier input VSWR is accounted for.

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