Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO 2 between the grains, the lateral charge loss is reduced and, thus, long retention time are possible. In this work we present good memory action characterised by low write voltages, write times of the order of milliseconds and long retention time in spite of the low tunnel oxide thickness. © 2002 Elsevier Science B.V. All rights reserved.
|Numero di pagine||4|
|Rivista||MATERIALS SCIENCE AND ENGINEERING. C, BIOMIMETIC MATERIALS, SENSORS AND SYSTEMS|
|Stato di pubblicazione||Published - 2003|
All Science Journal Classification (ASJC) codes
- Condensed Matter Physics
- Mechanics of Materials
- Mechanical Engineering