TY - CONF
T1 - Efficient FPGA Implementation of an Adaptive Noise Canceller
AU - Giaconia, Giuseppe Costantino
AU - Di Stefano, Antonio
PY - 2005
Y1 - 2005
N2 - A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.
AB - A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.
KW - Bioelectric potentials
KW - Electroencephalography
KW - Evoked Potentials
KW - Bioelectric potentials
KW - Electroencephalography
KW - Evoked Potentials
UR - http://hdl.handle.net/10447/18294
M3 - Other
SP - 87
EP - 89
ER -