Non volatile memories based on Si nanocrystals (Si-ncs) offer an important alternative to conventional floating gate devices, for the numerous potential advantages associated with the discrete-trap structures . Isolated Si-ncs can be obtained by chemical vapor deposition (CVD) through a fully compatible CMOS process. So far, the main limitation for scaling the CVD Si-nc memories at sub-90 nm node is related to the expected fluctuation, from bit to bit, in the device threshold voltage (VTH), due to the spread in the sur- face fraction (Rdot) covered with Si dots . The reason is the assumption that the dot position and the relative distance are fully random. It will be shown that the nucleation proc- ess is not purely random and the dot formation evolves with partial self-ordering. The relative dispersion of Rdot is nu- merically evaluated as a function of gate size, for random and partially self-ordered nucleation processes. The result is compared to data on VTH distribution and extrapolated to small gate areas.
|Numero di pagine||2|
|Stato di pubblicazione||Published - 2004|