Design of MOS current mode logic gates - Computing the limits of voltage swing and bias current

    Risultato della ricerca: Otherpeer review

    5 Citazioni (Scopus)

    Abstract

    Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we will show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.
    Lingua originaleEnglish
    Pagine5637-5640
    Numero di pagine4
    Stato di pubblicazionePublished - 2005

    All Science Journal Classification (ASJC) codes

    • Electrical and Electronic Engineering

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