Design exploration of aes accelerators on FPGAS and GPUs

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1 Citazione (Scopus)

Abstract

The embedded systems are increasingly becoming a key technological component of all kinds of complex tech-nical systems and an exhaustive analysis of the state of the art of all current performance with respect to architectures, design methodologies, test and applications could be very in-teresting. The Advanced Encryption Standard (AES), based on the well-known algorithm Rijndael, is designed to be easily implemented in hardware and software platforms. General purpose computing on graphics processing unit (GPGPU) is an alternative to recongurable accelerators based on FPGA devices. This paper presents a direct comparison between FPGA and GPU used as accelerators for the AES cipher. The results achieved on both platforms and their analysis has been compared to several others in order to establish which device is best at playing the role of hardware accel-erator by each solution showing interesting considerations in terms of throughput, speedup factor, and resource usage. This analysis suggests that, while hardware design on FPGA remains the natural choice for consumer-product design, GPUS are nowadays the preferable choice for PC based ac-celerators, especially when the processing routines are highly parallelizable.
Lingua originaleEnglish
pagine (da-a)28-38
Numero di pagine11
RivistaJournal of Telecommunications and Information Technology
Volume2017
Stato di pubblicazionePublished - 2017

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Particle accelerators
Field programmable gate arrays (FPGA)
Hardware
Cryptography
Consumer products
Product design
Embedded systems
Throughput
Processing
Graphics processing unit

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cita questo

@article{f007a7d920964d52b0422610f64fce84,
title = "Design exploration of aes accelerators on FPGAS and GPUs",
abstract = "The embedded systems are increasingly becoming a key technological component of all kinds of complex tech-nical systems and an exhaustive analysis of the state of the art of all current performance with respect to architectures, design methodologies, test and applications could be very in-teresting. The Advanced Encryption Standard (AES), based on the well-known algorithm Rijndael, is designed to be easily implemented in hardware and software platforms. General purpose computing on graphics processing unit (GPGPU) is an alternative to recongurable accelerators based on FPGA devices. This paper presents a direct comparison between FPGA and GPU used as accelerators for the AES cipher. The results achieved on both platforms and their analysis has been compared to several others in order to establish which device is best at playing the role of hardware accel-erator by each solution showing interesting considerations in terms of throughput, speedup factor, and resource usage. This analysis suggests that, while hardware design on FPGA remains the natural choice for consumer-product design, GPUS are nowadays the preferable choice for PC based ac-celerators, especially when the processing routines are highly parallelizable.",
author = "Vincenzo Conti and Salvatore Vitabile and Vincenzo Conti",
year = "2017",
language = "English",
volume = "2017",
pages = "28--38",
journal = "Journal of Telecommunications and Information Technology",
issn = "1509-4553",
publisher = "National Institute of Telecommunications",

}

TY - JOUR

T1 - Design exploration of aes accelerators on FPGAS and GPUs

AU - Conti, Vincenzo

AU - Vitabile, Salvatore

AU - Conti, Vincenzo

PY - 2017

Y1 - 2017

N2 - The embedded systems are increasingly becoming a key technological component of all kinds of complex tech-nical systems and an exhaustive analysis of the state of the art of all current performance with respect to architectures, design methodologies, test and applications could be very in-teresting. The Advanced Encryption Standard (AES), based on the well-known algorithm Rijndael, is designed to be easily implemented in hardware and software platforms. General purpose computing on graphics processing unit (GPGPU) is an alternative to recongurable accelerators based on FPGA devices. This paper presents a direct comparison between FPGA and GPU used as accelerators for the AES cipher. The results achieved on both platforms and their analysis has been compared to several others in order to establish which device is best at playing the role of hardware accel-erator by each solution showing interesting considerations in terms of throughput, speedup factor, and resource usage. This analysis suggests that, while hardware design on FPGA remains the natural choice for consumer-product design, GPUS are nowadays the preferable choice for PC based ac-celerators, especially when the processing routines are highly parallelizable.

AB - The embedded systems are increasingly becoming a key technological component of all kinds of complex tech-nical systems and an exhaustive analysis of the state of the art of all current performance with respect to architectures, design methodologies, test and applications could be very in-teresting. The Advanced Encryption Standard (AES), based on the well-known algorithm Rijndael, is designed to be easily implemented in hardware and software platforms. General purpose computing on graphics processing unit (GPGPU) is an alternative to recongurable accelerators based on FPGA devices. This paper presents a direct comparison between FPGA and GPU used as accelerators for the AES cipher. The results achieved on both platforms and their analysis has been compared to several others in order to establish which device is best at playing the role of hardware accel-erator by each solution showing interesting considerations in terms of throughput, speedup factor, and resource usage. This analysis suggests that, while hardware design on FPGA remains the natural choice for consumer-product design, GPUS are nowadays the preferable choice for PC based ac-celerators, especially when the processing routines are highly parallelizable.

UR - http://hdl.handle.net/10447/236783

UR - http://www.itl.waw.pl/czasopisma/JTIT/2017/1/28.pdf

M3 - Article

VL - 2017

SP - 28

EP - 38

JO - Journal of Telecommunications and Information Technology

JF - Journal of Telecommunications and Information Technology

SN - 1509-4553

ER -