Design and Implementation of an Efficient Fingerprint Features Extractor

Risultato della ricerca: Otherpeer review

2 Citazioni (Scopus)

Abstract

Biometric recognition systems are rapidly evolvingtechnologies and their use in embedded devices for accessing andmanaging data and resources is a very challenging issue. Usually,they are composed of three main modules: Acquisition, FeaturesExtraction and Matching. In this paper the hardware design andimplementation of an efficient fingerprint features extractor forembedded devices is described. The proposed architecture,designed for different acquisition sensors, is composed of fourblocks: Image Pre-processor, Macro-Features Extractor, Micro-Features Extractor and Master Controller. The Image Preprocessorblock increases the quality level of the input raw imageand performs an adaptive binarization, introducing a novelhardware approach. The Macro-Features Extractor extractssingularity points. The Micro-Features Extractor extracts onlymicro-features around singularity points using an adaptivethinning and a post-processing phase to remove potential falsemicro-features. The Master Controller synchronizes andcoordinates the two extractors. Xilinx ML507 board has beenused to develop the prototype, while tests have been conducted onthe PolyU (Hong Kong Polytechnic University) and the FVC2002DB2-B free databases. These two databases have been chosen fortheir different characteristics in terms of image resolution anddimension in order to test the effectiveness of the proposedarchitecture. Experimental results show an interesting trade-offbetween used resources (about 32%) and fingerprint featuresextraction time (the lower execution time is 21.6 ms while thehigher execution time is 28.4 ms, with a working frequency of 25MHz), obtaining the best rate of false minutiae discharged of 5%.
Lingua originaleEnglish
Numero di pagine5
Stato di pubblicazionePublished - 2014

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Information Systems
  • Hardware and Architecture

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