Analysis of compressor architectures in MOS current-mode logic

This paper is concerned with the design and the comparison of different compressor architectures for high performance multipliers in MOS current-mode logic (MCML). More specifically, three architectures have been designed for 3-2,4-2 and 5-2 compressors and two architectures for 7-2 compressors. The various implementations for each type ofcompressor have been compared one another. This investigation indicates that the architectures based exclusively on three-level MCML gates are the most suitablefor MCML implementation in terms of speed, power consumption and area. Design guidelines are provided to improve compressor performance. All the compressors were designed in a TSMC 180nm CMOS technology.