Analysis of compressor architectures in MOS current-mode logic

Di Sclafani, D

    Risultato della ricerca: Paper

    7 Citazioni (Scopus)

    Abstract

    This paper is concerned with the design and the comparison of different compressor architectures for high performance multipliers in MOS current-mode logic (MCML). More specifically, three architectures have been designed for 3-2, 4-2 and 5-2 compressors and two architectures for 7-2 compressors. The various implementations for each type of compressor have been compared one another. This investigation indicates that the architectures based exclusively on three-level MCML gates are the most suitable for MCML implementation in terms of speed, power consumption and area. Design guidelines are provided to improve compressor performance. All the compressors were designed in a TSMC 180nm CMOS technology.
    Lingua originaleEnglish
    Stato di pubblicazionePublished - 2010

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    Compressors
    Logic gates
    Electric power utilization

    All Science Journal Classification (ASJC) codes

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cita questo

    Analysis of compressor architectures in MOS current-mode logic. / Di Sclafani, D.

    2010.

    Risultato della ricerca: Paper

    @conference{076b2dd2d1e34662ab0bbb0ae73c2619,
    title = "Analysis of compressor architectures in MOS current-mode logic",
    abstract = "This paper is concerned with the design and the comparison of different compressor architectures for high performance multipliers in MOS current-mode logic (MCML). More specifically, three architectures have been designed for 3-2, 4-2 and 5-2 compressors and two architectures for 7-2 compressors. The various implementations for each type of compressor have been compared one another. This investigation indicates that the architectures based exclusively on three-level MCML gates are the most suitable for MCML implementation in terms of speed, power consumption and area. Design guidelines are provided to improve compressor performance. All the compressors were designed in a TSMC 180nm CMOS technology.",
    keywords = "Compressors, multipliers, MOS current-mode logic",
    author = "{Di Sclafani, D} and Giuseppe Caruso",
    year = "2010",
    language = "English",

    }

    TY - CONF

    T1 - Analysis of compressor architectures in MOS current-mode logic

    AU - Di Sclafani, D

    AU - Caruso, Giuseppe

    PY - 2010

    Y1 - 2010

    N2 - This paper is concerned with the design and the comparison of different compressor architectures for high performance multipliers in MOS current-mode logic (MCML). More specifically, three architectures have been designed for 3-2, 4-2 and 5-2 compressors and two architectures for 7-2 compressors. The various implementations for each type of compressor have been compared one another. This investigation indicates that the architectures based exclusively on three-level MCML gates are the most suitable for MCML implementation in terms of speed, power consumption and area. Design guidelines are provided to improve compressor performance. All the compressors were designed in a TSMC 180nm CMOS technology.

    AB - This paper is concerned with the design and the comparison of different compressor architectures for high performance multipliers in MOS current-mode logic (MCML). More specifically, three architectures have been designed for 3-2, 4-2 and 5-2 compressors and two architectures for 7-2 compressors. The various implementations for each type of compressor have been compared one another. This investigation indicates that the architectures based exclusively on three-level MCML gates are the most suitable for MCML implementation in terms of speed, power consumption and area. Design guidelines are provided to improve compressor performance. All the compressors were designed in a TSMC 180nm CMOS technology.

    KW - Compressors, multipliers, MOS current-mode logic

    UR - http://hdl.handle.net/10447/53505

    M3 - Paper

    ER -