A Methodology for the Design of MOS Current-Mode Logic Circuits

Giuseppe Caruso, Alessio Macchiarella

    Risultato della ricerca: Article

    10 Citazioni (Scopus)

    Abstract

    In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process.
    Lingua originaleEnglish
    pagine (da-a)172-181
    Numero di pagine10
    RivistaIEICE Transactions on Electronics
    VolumeE93-C
    Stato di pubblicazionePublished - 2010

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    Logic circuits
    Electric power utilization
    Capacitance
    MATLAB
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    All Science Journal Classification (ASJC) codes

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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    A Methodology for the Design of MOS Current-Mode Logic Circuits. / Caruso, Giuseppe; Macchiarella, Alessio.

    In: IEICE Transactions on Electronics, Vol. E93-C, 2010, pag. 172-181.

    Risultato della ricerca: Article

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    AB - In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process.

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