A Design Methodology for Low-Power MCML Ring Oscillators

Macchiarella, A.

    Risultato della ricerca: Paper

    9 Citazioni (Scopus)

    Abstract

    In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method
    Lingua originaleEnglish
    Stato di pubblicazionePublished - 2007

    All Science Journal Classification (ASJC) codes

    • Computational Theory and Mathematics
    • Electrical and Electronic Engineering

    Cita questo

    A Design Methodology for Low-Power MCML Ring Oscillators. / Macchiarella, A.

    2007.

    Risultato della ricerca: Paper

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    abstract = "In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method",
    author = "{Macchiarella, A.} and Giuseppe Caruso",
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    AU - Macchiarella, A.

    AU - Caruso, Giuseppe

    PY - 2007

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    N2 - In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method

    AB - In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method

    UR - http://hdl.handle.net/10447/14590

    M3 - Paper

    ER -