This paper describes the low-power design of a MOS current-mode logarithmic adder. The adder utilizes the Brent-Kung tree structure. The design strategy adopted is very simple and effective. Moreover, it can be utilized also for other types of logarithmic adders. To validate it, several adders were designed in a TSMC CMOS 130nm technology. Results of simulations indicate that the proposed methodology offers a good starting point before fine-tuning the design by SPICE simulations. Finally, the tradeoff that can be realized between performance and power consumption is discussed.
|Number of pages||3|
|Publication status||Published - 2010|
All Science Journal Classification (ASJC) codes
- Signal Processing
- Electrical and Electronic Engineering