Optimum Design of Two-Level MCML Gates

Giuseppe Caruso, Alessio Macchiarella

    Research output: Contribution to conferenceOther

    6 Citations (Scopus)

    Abstract

    In this paper, we address the problem of the optimum design of two-level MOS Current Mode Logic (MCML) gates. In particular, we describe a design methodology based on the concept of crossing-point current already introduced for the optimum design of single-level MCML gates. This methodology is suited both for automated implementation and graphic estimate of the optimum design. Moreover, it clearly shows how some important design parameters affect the optimum values of delay and power consumption. Several gates were designed in an IBM 130nm CMOS technology. The results of SPICE simulations, reported here, demonstrate the effectiveness of the proposed design methodology.
    Original languageEnglish
    Pages141-144
    Publication statusPublished - 2008

    All Science Journal Classification (ASJC) codes

    • Electrical and Electronic Engineering

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