A Methodology for the Design of MOS Current-Mode Logic Circuits

Giuseppe Caruso, Alessio Macchiarella

    Research output: Contribution to journalArticlepeer-review

    10 Citations (Scopus)


    In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process.
    Original languageEnglish
    Pages (from-to)172-181
    Number of pages10
    JournalIEICE Transactions on Electronics
    Publication statusPublished - 2010

    All Science Journal Classification (ASJC) codes

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering


    Dive into the research topics of 'A Methodology for the Design of MOS Current-Mode Logic Circuits'. Together they form a unique fingerprint.

    Cite this